1. Field of the Invention
The present invention relates to a semiconductor chip having a protective circuit prepared for an input of an abnormal voltage or current supplied from the outside due to static electricity or the like, and also to a multichip-type semiconductor device having semiconductor chips each of which has the arrangement of the semiconductor chip above-mentioned.
2. Description of Related Art
In a multichip-type semiconductor device in which a plurality of semiconductor chips are being resin-molded as connected to one another, the mutual connection of the semiconductor chips is conducted in any of a variety of manners. For example, there are instances where the semiconductor chips are connected to one another by bonding wires. There are also instances where the semiconductor chips are piled up on one another to form a chip-on-chip structure and are electrically connected to one another through bumps. There are also instances where the semiconductor chips are bonded onto a printed circuit board, thus achieving the mutual electrical connection of the semiconductor chips.
Each of the semiconductor chips forming a multichip-type semiconductor device, is provided on the surface thereof with a plurality of pads for electrical connection with another semiconductor chips. The pads are connected to an internal circuit formed on a semiconductor substrate serving as the base body of the semiconductor chip. The semiconductor chip itself can also be used as a single element. In such a case, pads are connected to lead frames which are pulled out to the outside of the package.
FIG. 6 is a block diagram illustrating an electric arrangement relating to a pad 101 of a semiconductor chip 100. The pad 101 is connected to an internal circuit 103 through a wiring 102. In the vicinity of the pad 101, a diode 105 is connected to the wiring 102 between the same and the power line, while a diode 106 is connected to the wiring 102 between the same and the ground. These diodes 105, 106 form a surge protective circuit 104. This surge protective circuit 104 is arranged to absorb a surge entered through the pad 101 from the outside of the semiconductor chip 100, thus preventing the internal circuit 103 from being damaged.
There are instances where an excessive voltage is externally applied to the semiconductor chip 100. For example, an excessive voltage is applied when a functional test is conducted with a test probe applied to the pad 101, before the semiconductor chip 100 is assembled into a multichip-type semiconductor device. Further, when the semiconductor chip 100 itself is used as a single element, there is a likelihood that an excessive voltage due to static electricity is applied to the pad 101 through a lead frame. In such a case, the surge protective circuit 104 is actuated to protect the internal circuit 103.
However, the diodes 105, 106 accompany large parasitic capacitances C1, C2. Accordingly, when it is particularly intended to operate the semiconductor chip 100 at high speed, the power consumption is disadvantageously increased due to charge and discharge of the parasitic capacitances C1, C2. Further, when the large parasitic capacitances C1, C2 are connected to the wiring 102, there are instances where restrictions are imposed on the operational speed, resulting in a failure to achieve an operation at the target speed.
A similar trouble is also caused by a large parasitic capacitance accompanying with a driver circuit connected to a signal output pad. More specifically, there is interposed, between the signal output pad and an internal circuit, a driver circuit for driving a volt-ammeter used when a functional test is conducted or for driving an external wiring when the semiconductor chip itself is used as a single element. This driver circuit is not necessarily required when connecting, to one another, semiconductor chips in which a high electric current is not required to flow. However, the driver circuit cannot be eliminated in view of the need of a functional test. Accordingly, when a multichip-type semiconductor device is formed, large parasitic capacitances accompanying with the driver circuit inevitably introduce problems such as an increase in power consumption at a high-speed operation and a limited operational speed.
It is an object of the present invention to provide a semiconductor chip and a multichip-type semiconductor device each of which is capable of reducing the power consumption and achieving a high-speed operation.
A semiconductor chip according to the present invention comprises: an internal circuit formed on a semiconductor substrate; a chip connection pad formed on the semiconductor substrate and used for interchip connection to another semiconductor chip; an other-service-than-interchip-connection pad formed on the semiconductor substrate and used for other service than interchip connection; and a switching circuit formed on the semiconductor substrate for selectively connecting, to the internal circuit, the chip connection pad or the other-service-than-interchip-connection pad.
The xe2x80x9cinterchip connectionxe2x80x9d generally refers to the mutual connection of semiconductor chips to be encapsulated in the same package.
The other-service-than-interchip-connection pad may be a pad to which a test probe is connected when conducting a functional test for checking the operation of the semiconductor chip.
The other-service-than-interchip-connection pad may be a pad to which connected is a lead frame pulled out to the outside of the package. The other-service-than-interchip-connection pad may also be a pad commonly used for a test and for connection to the outside of the package.
According to the present invention, there are disposed the chip connection pad used for interchip connection and the other-service-than-interchip-connection pad used for other service than interchip connection, and these pads are selectively connected to the internal circuit by the switching circuit.
Therefore, for example, a protective circuit for protecting the internal circuit is preferably disposed as connected to the other-service-than-interchip-connection pad. According to the arrangement above-mentioned, when conducting a functional test on the semiconductor chip or when it becomes necessary to connect the internal circuit to the outside through the lead frame, the internal circuit is connected to the other-service-than-interchip-connection pad by the switching circuit and the other-service-than-interchip-connection pad is used. This enables the internal circuit to be protected against an abnormal input from the outside. On the other hand, when this semiconductor chip is connected to another semiconductor chip, the switching circuit is operated to connect the internal circuit to the chip connection pad to which the protective circuit is not connected. Thus, the internal circuit is not influenced by the parasitic capacitance accompanying with the protective circuit. This reduces the power consumption and achieves a high-speed operation.
Preferably, the parasitic capacitance accompanying with the chip connection pad is smaller than that accompanying with the other-service-than-interchip-connection pad.
For example, when the protective circuit is connected to the other-service-than-interchip-connection pad and such a protective circuit is not connected to the chip connection pad as done in the arrangement above-mentioned, the parasitic capacitance accompanying with the other-service-than-interchip-connection pad is large, and the parasitic capacitance accompanying with the chip connection pad is much smaller.
For example, when the semiconductor chip incorporates a driver circuit for driving a volt-ammeter for a functional test or an external wiring (mainly, a wiring outside of the package) to be connected through the lead frame, and this driver circuit is connected to the other-service-than-interchip-connection pad, there is present a large parasitic capacitance accompanying with this driver circuit. On the other hand, the chip connection pad is not required to have a driver circuit having such a high electric current as to drive an external wiring or the like. Thus, the parasitic capacitance accompanying with the chip connection pad is much smaller than the parasitic capacitance accompanying with the other-service-than-interchip-connection pad.
Therefore, the switching circuit is suitably switched such that the other-service-than-interchip-connection pad is connected to the internal circuit at the time of a functional test or connection to an external wiring, and that the chip connection pad is connected to the internal circuit at the time of interchip connection. Thus, at the time of interchip connection, the power consumption can be reduced and a high-speed operation can be achieved.
The switching circuit may be arranged to disconnect the internal circuit from the other-service-than-interchip-connection pad and connect the internal circuit to the chip connection pad when the semiconductor chip is being connected to another semiconductor chip through the chip connection pad, and may also be arranged to disconnect the internal circuit from the chip connection pad and connect the internal circuit to the other-service-than-interchip-connection pad when the semiconductor chip is not being connected to another semiconductor chip through the chip connection pad.
According to the arrangement above-mentioned, the chip connection pad is automatically connected to the internal circuit when the semiconductor chip is connected to another semiconductor chip, and the other-service-than-interchip-connection pad is automatically connected to the internal circuit when the semiconductor chip is not connected to another semiconductor chip. Therefore, for example, when the protective circuit is disposed as connected to the other-service-than-interchip-connection pad, the protective circuit can protect the internal circuit against an abnormal input from the outside when the semiconductor chip itself is used as a single element. Further, when the parasitic capacitance accompanying with the chip connection pad is smaller than that accompanying with the other-service-than-interchip-connection pad, an operation with a reduced power consumption and a high-speed operation can be expected when the semiconductor chip is being connected to another semiconductor chip.
Preferably, there is further disposed a switching control input pad formed, as connected to the switching circuit, on the semiconductor substrate, and arranged to receive a switching control signal for controlling the switching operation of the switching circuit.
According to the arrangement above-mentioned, the switching circuit can be switched by supplying a switching control signal from the switching control input pad.
Provision is preferably made such that the switching control input pad is connected to a pad which presents a predetermined voltage in another semiconductor chip, and that the switching circuit disconnects the internal circuit from the other-service-than-interchip-connection pad and connects the internal circuit to the chip connection pad, in response to an input of a predetermined voltage to the switching control input pad.
According to the arrangement above-mentioned, when the semiconductor chip is connected to another semiconductor chip, the predetermined voltage (for example, the power voltage or ground voltage) is given to the switching control input pad from another semiconductor chip. Accordingly, when the semiconductor chip is connected to another semiconductor chip, the chip connection pad can automatically be connected to the internal circuit.
A multichip-type semiconductor device of the present invention is formed by connecting a first semiconductor chip to a second semiconductor chip, the first semiconductor chip having a first chip connection pad used for interchip connection to the second semiconductor chip, the second semiconductor chip including: a second chip connection pad used for interchip connection to the first semiconductor chip; an other-service-than-interchip-connection pad used for other service than interchip connection; a switching circuit for selectively connecting, to an internal circuit of the second semiconductor chip, the second chip connection pad or the other-service-than-interchip-connection pad; and a switching control input pad for receiving a switching control signal for controlling the switching operation of the switching circuit, and the first semiconductor chip further having a switching control output pad to be connected to the switching control input pad for giving a switching control signal.
There may further be disposed interchip connection members for connecting the first and second chip connection pads to each other, and for connecting the switching control input pad and the switching control output pad to each other.
According to the arrangement above-mentioned, the interchip connection members may comprise a metal projection formed on the surface of the first and/or second chip connection pads, and a metal projection formed on the surface of the switching control input pad and/or the switching control output pad. Each of the metal projections may be a bump in the form of a thick layer formed by electrolytic plating or electroless plating, or may be a metal layer such as a metallized layer which is not so high as a bump. According to the arrangement above-mentioned, the connection between the first and second chip connection pads and the connection between the switching control input pad and the switching control output pad, are achieved by bonding the metal projections to each other or by bonding the metal projections and the pads to each other.
The interchip connection members may be bonding wires.
In the multichip-type semiconductor device of the present invention, the effects discussed in connection with the semiconductor chip above-mentioned can be produced for the second semiconductor chip. Accordingly, the multichip-type semiconductor device having the first and second semiconductor chips, can achieve an operation with a reduced power consumption and a high-speed operation.
Further, when a protective circuit is disposed in connection with the other-service-than-interchip-connection pad of the second semiconductor chip, a functional test can be conducted on the second semiconductor chip before the same is connected to the first semiconductor chip to form a multichip-type semiconductor device.
In the second semiconductor chip, the parasitic capacitance accompanying with the second chip connection pad is preferably smaller than that accompanying with the other-service-than-interchip-connection pad.
This contributes to a reduction in power consumption and a higher-speed operation of the multichip-type semiconductor device.
Provision is preferably made such that the switching circuit is arranged to disconnect the internal circuit from the other-service-than-interchip-connection pad and connect the internal circuit to the second chip connection pad when the switching circuit receives a switching control signal generated by the switching control output pad of the first semiconductor chip, and is also arranged to disconnect the internal circuit from the second chip connection pad and connect the internal circuit to the other-service-than-interchip-connection pad when the switching circuit does not receive a switching control signal generated by the switching control output pad of the first semiconductor chip.
According to the arrangement above-mentioned, the switching circuit can suitably automatically be switched.
The second semiconductor chip may be piled up on and bonded to the surface of the first semiconductor chip, and the first and second semiconductor chips may be bonded to each other in a chip-on-chip structure.
According to the arrangement above-mentioned, the wiring length (a connection member comprising a metal projection such as a bump) between the first and second chip connection pads is very short. This further reduces the power consumption and increases the operational speed.